We are looking for a Senior Photonic Device & Simulation Engineer to
join as one of the first hires in our startup. This person will own the
design, simulation, and experimental validation of high-speed
electro-optic modulators and related photonic building blocks for
photonic integrated circuits. This is not a narrow simulation-only role.
The right candidate should be able to move from device physics and
simulations to layout intent, foundry constraints, test structures,
lab data, model updates, and design decisions. You will work closely
with the founders and early engineering team to turn device concepts
into manufacturable, measurable, and scalable PIC designs.
Responsibilities:
Own the design and optimization of high-speed electro-optic modulators, including MZM, traveling-wave MZM, ring modulators, phase shifters, waveguides, couplers, transitions, and related active/passive photonic structures.
Build and maintain simulation workflows using Ansys Lumerical, or equivalent photonic simulation tools.
Model and optimize key high-speed modulator metrics, including EO bandwidth, Vπ, Vπ·L, insertion loss, extinction ratio, RF loss, impedance, velocity matching, S-parameters, optical loss, and process sensitivity.
Translate system-level and link-level requirements into photonic-device specifications.
Work with layout engineers or external layout resources to convert device designs into manufacturable PIC layouts, including clear layout intent, design rules, test structures, and review criteria.
Support compact-model development for device-, circuit-, and system-level simulations.
Run design-of-experiment, and tolerance studies to improve yield, robustness, and manufacturability.
Define and support wafer-level and packaged-device characterization, including DC, optical, EO, and RF measurements.
Compare measurement data with simulations, identify gaps, update models, and drive the next design iteration.
Work directly with foundries, packaging partners, RF/electrical engineers, and test engineers to resolve cross-domain design issues.
Contribute to the startup's core photonics IP, design methodology, simulation infrastructure, and technical roadmap.
Requirements:
M.Sc. or Ph.D. in photonics, electrical engineering, applied physics, optoelectronics, or related field.
Hands-on experience with Lumerical or equivalent photonic simulation tools.
Strong understanding of integrated optics, electro-optic modulation, waveguides, phase shifters, and high-speed photonic devices.
Experience with active photonic components such as modulators, photodiodes, or phase shifters.
Ability to work with layout engineers and foundry PDK constraints.
Preferred:
Traveling-wave modulator or RF photonics experience
HFSS, COMSOL, ADS, Spectre, Sentaurus, Silvaco, or similar tool experience
We are looking for a Senior PIC Layout & Tape-Out Engineer to join
as one of the first photonics hires in our startup. This person will
own the physical implementation of our photonic integrated circuits,
from early layout exploration through foundry-ready GDS, DRC/LVS
closure, mask review, and tape-out. This is a hands-on technical
ownership role. The right candidate should be able to work directly
with photonic device designers, RF/electrical engineers, packaging
engineers, test engineers, and foundry partners to turn device concepts
and circuit schematics into manufacturable, testable, and scalable
PIC layouts.
Responsibilities:
Own PIC layout implementation from concept through tape-out, including block-level layout, chip-level floorplanning, hierarchy, routing, verification, and final GDS/OASIS preparation.
Translate photonic-device specifications, schematics, and layout intent into manufacturable layouts for waveguides, couplers, MZIs, rings, modulators, photodetectors, heaters, grating couplers, edge couplers, test structures, and optical routing.
Create and maintain reusable PCells and layout libraries for key photonic building blocks such as waveguides, bends, tapers, couplers, splitters, modulators, gratings, pads, and test structures.
Perform waveguide routing while meeting optical-connectivity, bend-radius, spacing, loss, crosstalk, density, and process-design-rule constraints.
Integrate photonic layouts with electrical and RF interfaces, including electrodes, heaters, pads, GSG structures, metal routing, ESD-related constraints, keepouts, and packaging interfaces.
Run, debug, and close DRC, LVS, optical connectivity, hierarchy, density/fill, and foundry signoff checks.
Prepare tape-out-ready GDS/OASIS data and support mask review, foundry submission, waiver discussions, and post-submission issue resolution.
Work with device and simulation engineers to make layout tradeoffs that preserve optical, RF, thermal, and manufacturing performance.
Build and improve the company's PIC layout methodology, including naming conventions, hierarchy rules, PCell standards, layout review checklists, tape-out documentation, and version-controlled design flows.
Support test-chip planning by creating layout structures for process monitors, cutbacks, calibration devices, RF/EO test structures, and wafer-probe access.
Help establish the startup's internal layout infrastructure so future designs become faster, cleaner, and less dependent on manual heroics.
Requirements:
B.Sc., M.Sc., or equivalent practical experience in electrical engineering, photonics, physics, microelectronics, or a related field.
Hands-on experience with custom IC or photonic IC layout.
Strong proficiency with Cadence Virtuoso or a comparable professional layout environment.
Experience working with foundry PDKs and design-rule manuals.
Hands-on experience running and debugging DRC and LVS.
Familiarity with GDSII/OASIS workflows, hierarchical layout, cell libraries, mask layers, layer maps, and tape-out preparation.
Understanding of photonic layout concepts, including waveguides, bends, tapers, grating couplers, edge couplers, splitters, MZIs, rings, heaters, modulators, and photodetectors.
Ability to translate incomplete or evolving design intent into clean, reviewable, manufacturable layout.
Experience with layout automation or scripting using Python, SKILL, KLayout, gdsfactory, IPKISS, Luceda, or similar tools.
Strong attention to detail and the ability to manage complex layouts under tape-out schedule pressure.
Comfort working in an early-stage startup environment where processes are still being built and engineers are expected to own problems end-to-end.
Preferred:
Prior silicon-photonics or integrated-photonics tape-out experience.
Experience with high-speed electro-optic PICs, including modulators, photodiodes, RF pads, transmission-line electrodes, or optical transceiver layouts.
Analog, RF, or mixed-signal layout background, especially in Cadence Virtuoso.
Experience with photonic LVS, optical-connectivity checking, custom DRC/LVS rule decks, or non-standard foundry signoff flows.
Experience creating and maintaining PCells for photonic components.
Experience with multiple silicon photonics, SiN, InP, TFLN, or heterogeneous-integration foundry platforms.
Experience with MPW shuttles, full-mask tape-outs, mask reviews, density/fill rules, process biasing, OPC-related constraints, and foundry waiver processes.
Familiarity with packaging-aware layout, including fiber attach, edge coupling, grating-coupler arrays, wirebond pads, flip-chip interfaces, RF launches, thermal constraints, and probe-card access.
Experience documenting layout methodology and enforcing design hygiene across a small team.
